Creating an Adder circuit

from nand import NAND_gate from not_gate import NOT_gate from and_gate import AND_gate from or_gate import OR_gate from xor_gate import XOR_gate def half_adder(a,b): s = XOR_gate(a,b) c = AND_gate(a,b) return (s,c) #print(half_adder(0,0)) #print(half_adder(0,1)) #print(half_adder(1,0)) #print(half_adder(1,1)) #FULL ADDER def full_adder(a,b,c): sum1 = XOR_gate(a,b) sum2 = XOR_gate(sum1, c) c_out = OR_gate(sum1, sum2) return (sum2, c_out) print(full_adder(0,0,0)) print(full_adder(1,1,1)) print(full_adder(0,1,1)) print(full_adder(1,1,0))

What is wrong with this code? I am struggling with writing a c output…I get 0 at the last print of the function. Why? I should get 1

Did you mean to use XOR_gates in full_adder.
If you did then c_out will be 1 when;
A and B are 1 or when c and the result of XOR(a, b) are 1.

If you meant them to be half_adder, then c_out will be the carry from either sum1 or sum2. (Bear in mind half_adder returns two values.)

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hm…I don’t quite get it. I followed the instructions. Yes I meant to use XOR_gates… if you could just type the solution I would really apreciate it. I lost 2 hours on this, and I doubt it is productive to sit another 2h not having a clue what to do. Ima loose my mind here

No worries. It took me a while and I ended up looking up full adders on some wiki before I finally caught on.

At about line 36 (i.e between sum2 and c_out);
c1 = AND_gate( a, b)
c2 = AND_gate( sum1, c)
and then change the c_out = line to,
c_out = OR_gate( c1, c2)

I believe that should work.
If not, let us know and I’ll check back over what I did again.
Good luck

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everything before line 36 is okay in the code?

It works! Thanks for your help, I googled adder and looked at some pictures of logic gates drawing it is pretty straightforward…

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I don’t think the instructions for this one are particularly clear. Makes it feel far more complicated than it actually is.

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I actually did THIS and it worked…I could not figure out how to use the two half adders and an OR precisely as Step 6 directed, but my fx recreated the entire truth table.

def full_adder(a, b, c):

 s = half_adder(half_adder(a,b)[0], c)[0]
 c_out = OR_gate(half_adder(a,b)[1], half_adder(half_adder(a,b)[0], c)[1])
 return (s, c_out)

I tested my adder circuit and this appeared in the output console:
<function half_adder at 0x7feb51f1be18>
I had checked over the code and cleaned up the syntax. I should be getting 00, 01, 10, and 11. What am I missing?

Just sunk 2.5 hrs into this. It took me a while to even understand the problem correctly. Turns out someone above got the same answer as I did but I didn’t understand the logic when I first saw it.

c_out = OR_gate(half_adder(a, b)[1], half_adder(half_adder(a, b)[0], c)[1])

When summing (a + b + c) from left to right, either (a + b) or (a+b) + c has a carry. So we can use an OR_gate to determine if either sum has a carry or if both do not.